Literature Review of Fault Tolerant Systems

CHAPTER-2

PROBLEM STATEMENT

Aim of the undertakingis to build Fault Tolerant System. Fault Tolerant system is a system which runs efficaciously in any status. Even if there is a mistake in the processor our system will observe it and advise to user or admin. It will non merely notify but we are seeking that it will take mistake over the air. Triple Modular Redundancy is bosom of our system ; it detects the mistake through vote system.

To build a CFTP design is a truly complex work and needs a important sum of clip to complete. In order to hold a flawless design, tonss of conditions need to be considered and all jobs should be solved in a sensible manner. Choosing constituents may take few yearss or months depending on how much information or information is collected. Decisions may still be changed at the last minute due to some unpredictable state of affairss or inevitable factors. Any alteration in the concluding design on a constituent sometimes will do a series of alterations to others. It is obvious that constructing a fully-functional CFTP does take much attempt and interior decorators have to truly understand how circuits relate each other in order to revise or debug it. Unfortunately, graduate pupils at Naval Postgraduate School merely stay a short sum of clip. A large design like CFTP is chopped into several sections and assigned to different pupils. In this clip restraints, pupils non merely necessitate to recognize what old pupils have done but besides take up a design in advancement. Largely, pupils picking up the sections do non hold a opportunity to larn straight from pupils who have worked on this design earlier. Therefore, thesis becomes an of import interface of experience heritage between coevalss of pupils.

CHAPTER-3

LITERATURE REVIEW

3.1 LITERATURE SURVEY: –

3.1.1. Lashomb’s Design

Peter A. LaShomb expressed many constructs in both TMR design and FPGA choice. Traditional solutions for radiation effects were introduced including hardware redundancy, like Quadded Logic, and package betterment for mistake tolerance, like clip redundancy or package redundancy. In the TMR subdivision, RADHARD and COTS were compared in handiness, public presentation and cost. Potential benefits of those two were clearly described as good. The processor used in his TMR design was KCPSM, an 8-bit microcontroller. It was free downloaded from Xilinx’s web site and served as a readily available test-case processor while waiting handiness of other high public presentation processors. Constructing and testing of the TMR were done on Xilinx Foundation series package which was available at Naval Postgraduate School ( NPS ) . Voters and an mistake encoder were designed and explained in item. Other issues including interrupt modus operandi and memory/error accountant were left as follow-on research. In the FPGA subdivision, different FPGAs were compared in a figure of facets. Five major parametric quantities for taking a good FPGA were gate count, handiness of hardware and package, bundles ( flat-pack vs. ball-grid-array ) , re-programmability and radiation tolerance. The Xilinx XCV800 was chosen as the campaigner at that clip for future execution [ 25 ] .

3.1.2. Ebert’s Research

A complete CFTP conceptual design presented was in Dean A. Ebert’s thesis. For hardware considerations, his thesis discussed why specific constituents were chosen and how french friess communicated in an incorporate circuit. More item and realistic constructs about FPGA and CFTP constellations were described than earlier and french friess were selected based on a figure of space-environment considerations. Discussion of system memory was of import and first described in this thesis. Memory constellation accountant, functional logic and glue logic were besides new thoughts ne’er talked about in old work. The TMR circuitry was non one of the chief subjects in his research, but from his work one can visualise the external connexions of the FPGA and understand the function of TMR in the CFTP procedure. Figure 4 illustrates the layout of the board he developed The CFTP will be launched into LEO orbit on two orbiters, NPSAT-1 and Mid- STAR-1, in 2006. How the Department of Defense and Navy Space Experiment Review Board ( SERB ) and the Space Test Program ( STP ) Office were involved with these two orbiters was described in his thesis. Other paperss related to plan descriptions and demands of the STP office were attached every bit appendixes as good [ 26 ] .

3.1.3. Johnson’s Implementation

Steven A. Johnson [ 5 ] focused his work on TMR design. The indispensable constituents to do a circuit be fault-tolerant were identified. Circuits designed in Lashomb’s thesis could non be used due to different design architecture and the important ascent of computer-aided-design package employed. Basic constructs for building a TMR circuit were still the same, but implemented in a different manner. All processor end product signals have to be voted. Interrupt was compiled in a province diagram and used to trip the interrupt service modus operandi to rectify an mistake inside the processor.ESSDwas used to salvage the mistake syndrome in order to offer a log file for analysis. The off-chip memory for the CFTP is Von Neumann architecture. The Von Neumann architecture has merely one reference coach and one information coach. Due to this difference, aConciliatorwas designed to organize different timing restraints in order to do a proper read and compose on memory.

Normally, TMR communicates withConciliatorin order to entree memory. Meanwhile, the syndrome informations is latched intoESSDirrespective of an mistake happening or non. When an mistake occurs, a signal will be sent to disrupt and starts the Interrupt Service Routine ( ISR ) . At this minute, KDLX is stalled andESSDsaves the mistake syndrome to memory throughConciliator. Then interrupTgenerates a TRAP direction to KDLX and leads the whole circuit into an mistake rectification status. When KDLX sees the TRAP direction, it jumps to a specific memory location and the plan counter value before the leap is saved in an interrupt reference registry ( IAR ) , a particular registry inside KDLX. In the mistake rectification status, the contents of all registries inside KDLX are saved to memory through electors. Then, each registry is reloaded from memory. The intent for making this measure is to rectify any incompatibilities of the registries in all three KDLX processors. Since all contents have to go through electors while salvaging, any mistake inside any registry will be corrected [ 26 ] .

3.1.4. N-Modular

Keun Soo Yim, et.al. [ 8 ] nowadayss fault-tolerant, programmable elector architecture for software-implementedNitrogen-tuple modular redundant ( NMR ) computing machine systems. Software NMR is a cost-effective solution for high-performance, mission-critical computing machine systems because this can be built on top of commercial off-the-shelf ( COTS ) devices. Due to the big volume and entropy of voting informations, package NMR system requires a programmable elector. Our experiment shows that voting package that executes on a processor has the time-of-check-to-time-of-use ( TOCTTOU ) exposures and is unable to digest long continuance mistakes. In order to turn to these two jobs, we present a special-purpose elector processor and its embedded package architecture. The processor has a set of new instructions and hardware faculties that are used by the package in order to speed up the vote package executing and turn to the identified two dependability jobs. We have implemented the presented system on an FPGA platform. Our rating consequence shows that utilizing the presented system reduces the executing clip of mistake sensing codifications ( normally used in voting package ) by 14 % and their codification size by 56 % . Our mistake injection experiments validate that the presented system removes the TOCTTOU exposures and recovers under both transient and long continuance mistakes. This is achieved by utilizing 0.7 % excess hardware in a baseline processor [ 27 ] .